This invention is in the field of integrated circuit architecture. Embodiments of this invention are more specifically directed to generation of internal clock signals in large scale integrated circuits.
Advances in semiconductor technology in recent years have reduced the minimum feature sizes of semiconductor devices in integrated circuits. These advances have correspondingly increased the functionality of very large-scale integrated circuits for a given chip area, such that a single modern integrated circuit can now contain over one billion transistors, and can carry out multiple complex functions into integrated circuit. In addition, these reductions in device feature sizes, such as metal-oxide-semiconductor (MOS) transistor gates, also serve to increase the switching speed of those devices and the overall performance of the integrated circuit.
Internal operations in these large scale integrated circuits, particularly those involving digital logic, are typically clocked. Some integrated circuits receive an external timing reference, such as a crystal oscillator or an externally generated clock signal, from which clock signals can be derived, particularly for those operations such as input and output that synchronous with external functions. Internal functions within the integrated circuit, such as those functions that are carried out within an external clock, are typically based on internally-generated clock signals. Examples of conventional internal clock generator circuits include oscillators, frequency synthesizers, and the like, along with associated frequency divider or clock multiplier functions. Examples of internal functions controlled by such internal clock signals include the timing of signals involved in accessing selected memory cells in a memory array in the integrated circuit. Different memory technologies (e.g., static random access memory (RAM), non-volatile RAM or read-only memory (ROM), dynamic RAM, etc.) may be implemented in the same large scale integrated circuit, and may require control signals with different timing.
As fundamental in the art, the electrical behavior of solid-state components, such as MOS transistors, varies depending on certain parameters. Variations in the fabrication process, for example variations in MOS transistor gate width or threshold voltage, will be reflected in the electrical performance of transistors and other components. The operating conditions of the integrated circuit, including the power supply voltage and the operating temperature, also result in variations in electrical performance. For example, the switching speed of transistors in the integrated circuit will vary with power supply voltage, operating temperature, and variations in fabrication process parameters.
For those integrated circuits in which internal functions are clocked by internal clocks, these variations in device performance affect both internal clock generator circuits and the circuits controlled by those clock generator circuits. It has been observed that internal timing may vary, due to these causes, by as much as 100% between the fastest “corner” of the process, voltage, and temperature (i.e., the combination of process parameters, power supply voltage, and operating temperature meeting specification limits that results in the fastest transistor switching speed) and the slowest “corner”. While this variation in internal timing must be dealt with in the design of the integrated circuit, the matching of device sizes and attributes in modern complementary MOS (CMOS) integrated circuits generally allow the various circuit functions within the same device to “track” one another over these variations in process, voltage, and temperature. In other words, the various delay and switching times within the same integrated circuit tend to track one another over variations in process, temperature, and voltage. This tracking among devices in the same integrated circuit provides robustness in the overall integrated circuit operation over these variations.
A recently developed technology for realizing non-volatile solid-state memories in integrated circuits involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead zirconate titanate (PZT) or strontium-bismuth-tantalate (SBT), rather than silicon dioxide or silicon nitride as typically used in non-ferroelectric capacitors. Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits, for example by placing capacitors above the transistor level, between overlying levels of metal conductors. As a result, ferroelectric technology is now utilized in non-volatile solid-state read/write random access memory (RAM) devices. These memory devices, commonly referred to as “ferroelectric RAM”, or “FeRAM”, or “FRAM” devices, are now commonplace in many electronic systems, particularly portable electronic devices and systems, and are especially attractive for implantable medical devices such as pacemakers and defibrillators. Various memory cell architectures including ferroelectric capacitors are known in the art, including the 1T-1C (one transistor, one capacitor) arrangement, similar to conventional dynamic RAM memory cells, the 2T-2C (two transistor, two capacitor) cells in which the two ferroelectric capacitors in a cell are polarized to complementary states, and also in a “6T” CMOS static RAM cells in which ferroelectric capacitors coupled to each storage node can be programmed with the stored data state. As known in the art, the state of a ferroelectric memory cell is read by interrogating the capacitance of the ferroelectric capacitors to discern its polarization state, specifically by detecting the polarization capacitance (i.e., charge storage) that occurs upon application of a voltage above the coercive voltage. When the memory state is opposite that of the applied voltage, that voltage will cause the capacitor to change its polarization state, which appears as a relatively high capacitance. But when the memory state matches that of the applied voltage, that voltage exhibits little capacitance due to polarization, since its ferroelectric domains are already aligned in the direction of the applied coercive voltage, causing little additional polarization charge to be stored.
Unfortunately, it has been observed that the switching behavior of ferroelectric capacitor does not necessarily track that of conventional CMOS devices over variations in process, voltage, and temperature. In particular, it has been observed that the polarization charge of the ferroelectric capacitor at cold temperature (−40° C.) is reduced because the coercive voltage of the material increases with decreasing temperature, which weakens the stored state. In addition, the time required to “extract” the polarization charge (i.e., read the memory state of the ferroelectric capacitor) increases with decreasing temperature. As such, cold temperature operation of ferroelectric memory results in a read signal that is both weaker and slower, as additional time is necessary to develop a data signal for detection by the sense amplifiers in the memory. In contrast, cold temperature decreases switching times and propagation delays in CMOS circuits, including internal clock generators, sense amplifiers, and other circuits involved in the access of FRAM memory cells. This mismatch between the faster operation of CMOS circuits and the slower response by the ferroelectric cells requires additional delay to be designed into the sense operation to ensure functionality at cold temperature. But this additional delay will further slow the memory operation at the high temperature operating corner at which the CMOS circuits are already at their slowest, which pushes out the access and cycle times of the memory.